Low Energy Digit-serial Architectures for large GF(2m) multiplication
F. Allah Cherigui, D. Mlynek · 2001
Abstract. T his paper presents two low-energy, highly regular, VLSI architectures performing a large prime GF(2m) multiplication. The first one is area-efficient digit-serial architecture, when field-generating polynomial p(x) is a trinomial. The second architecture is digit-serial, programmable on p(x). Both architectures are suitable for computing large prime GF(2m) exponentiation for DL based schemes. The parallel algorithm inside of each digit cell reduces both the global cycle time for the first architecture and the switching activity in the second one. An analysis of the performance comparison is described as function of the digit-size. A comparison is made with the bit serial architecture based on the performance improvement with respect to computation delay and energy consumption of one multiplication operation. Thus, the factor of merit for performance measurement is defined as the product of energy times the delay and it is computed. The simulation results on gate level implementations shows that the energy delay products are highly reduced for both architectures. Therefore, the proposed architectures are attractive for low-power applications.