Multi-stacked 1G cell/layer Pipe-shaped BiCS Flash Memory
Takashi Maeda, Kiyotaro Itagaki, Tomoo Hishida, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, M. Kido, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Yoshihisa Iwata, Yohji Watanabe · 2009
A three-dimensional 16 stacked 1G cell/layer Pipe-shaped Bit-Cost Scalable (P-BiCS) flash memory test chip with 60nm technology has been developed. The effective 1-bit cell size is 0.00082 um2. This paper describes the branched control gate configuration and the new erase operation which are suitable for P-BiCS flash memory. P-BiCS flash memory is one of the most promising candidates for realizing the future T-bit storage device.