Architecture of a hardware module for MPEG-4 shape decoding
Mladen Bereković, K.A. Jacob, P. Pirsch · 2003
MPEG-4 shape coding comprises context based binary arithmetic encoding (CAE) as its centerpiece. The architecture of a dedicated hardware acceleration module for CAE shape decoding is presented. Synthesis with a 3LM 0.5 /spl mu/ CMOS library provides a size estimate of 9200 gates plus 3 KB of ROM, which equals approximately 5 mm/sup 2/ silicon area. The module achieves a throughput rate of 63 MPixel/s.