An incremental synthesis method for ASIC design
J.-C. Giomi · 2003
An incremental synthesis method which enables ASIC designers to incrementally modify their register-transfer-level (RTL) behavior descriptions is described. This synthesis method synthesizes and optimizes only RTL behaviors which have been modified. An incremental synthesis approach reduces the overall synthesis time when an incremental modification has been performed. This synthesis method allows ASIC designers to control the design space exploration more closely.>