Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits
S.F. Oakland · 2002
This paper addresses four issues associated with using IEEE Standard 1149.1 on system-on-a-chip integrated circuits (SOC ICs). First, a new, simplified method for accessing debug registers in processor cores embedded within ICs is presented. Second, structural information required by hardware/software processor development tools is presented. Third, issues associated with boundary-scan description language (BSDL) are discussed. Finally, high-speed boundary-scan cells that avoid a multiplexer delay are presented.