A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface
Chulbum Kim, Jinho Ryu, Taesung Lee, Hyunggon Kim, Jaewoo Lim, Jaeyong Jeong, Seonghwan Seo, Hongsoo Jeon, Bokeun Kim, Inyoul Lee, Dooseop Lee, Pansuk Kwak, Seong-Soon Cho, Yong-Sik Yim, Changhyun Cho, Woopyo Jeong, Kwangil Park, Jin-Man Han, Duheon Song, Kye-Hyun Kyung · IEEE Journal of Solid-State Circuits · 2012
A monolithic 64 Gb MLC NAND flash based on 21$~$nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed.