Efficient matrix multiplications on a concurrent data-loading array processor
Ming-Yang Chern, Tadao Murata · Proceedings of the International Conference on Parallel Processing · 1983
The authors introduce a VLSI-compatible architecture called the concurrent data-loading array processor (CDLAP). Many matrix operations on systolic arrays have the matrix data reshaping problem. The CDLAP can execute the multiplication for dense matrices without data reshaping. A partitioned multiplication algorithm is also presented for matrices larger than the array size. Based on the design in this paper, the utilization of processing elements is virtually the best achievable for large matrices. The CDLAP, with small variations, can be used for band matrix multiplications. The performance, taking into account the total computation time and data transfer bandwidth, is found better than systolic arrays. 11 references.