Design of a multistage decimation-interpolation filter
V. Gregers Hansen · 2005
A 2 chip digital multi-rate FIR filter implemented in 2 micron CMOS performs 10 million multiplications and 20 million accumulations per second. The filter has 48 programmable bandwidths in a 1-2-5 sequence, and can either interpolate or decimate. This paper describes the design and implementation of the filter.