A DFT technique for low frequency delay fault testing in high performance digital circuits
Bhaskar Chatterjee, Manoj Sachdev, Ali Reza Keshavarzi · 2003
This paper presents a DFT (design-for-testability) technique for delay fault testing of high performance, dynamic CMOS circuits. A high performance, delay fault testable, 16 bit adder is designed in 0.18 /spl mu/m CMOS technology. Simulations for the adder demonstrate that this technique can detect delay faults greater than 35 ps and improves delay fault detection capability. It also allows at least 10/spl times/ reduction in test mode clock frequency. Furthermore, the proposed method is capable of providing delay fault diagnostics. However, the proposed DFT technique increases delay by 8.6% with minimal power penalty.