Verilog HDL based FPGA design
G. Gannot, M. Ligthart · 2002
This paper presents a logic synthesis system for field programmable gate arrays (FPGAs) based on the Verilog HDL. It describes aspects of synthesis and optimization specific to FPGAs, in contrast to CMOS gate-arrays. Particular attention is paid to architecture specific optimization, both on register transfer and logic level. The concept of the design methodology is proven by a real-world implementation of an actual design.>