A 250 MHz CMOS floating-point divider with operand pre-scaling
Shutaro Inui, Tadayuki Uesugi, Harukazu Saito, Y. Hagihara, A. Yoshikawa, M. Nishida, M. Yamashina · 2003
High performance floating-point (FP) dividers are essential arithmetic units for graphics applications and simulations, and various algorithms and implementation techniques have been proposed. Using a 0.25 /spl mu/m CMOS technology, we have developed an FP divider, which supports IEEE-754 single-precision and double-precision formats. By using conventional static CMOS logic and (a) a radix-4 SRT algorithm (from the initials of Sweeny, Robertson and Tocher, who developed this algorithm at the same time) with a maximally redundant digit set, (b) a partially nonredundant remainder scheme and (c) a simple operand pre-scaling; the divider can calculate 4 quotient digits/cycle at over 250 MHz with a 2.5 V power supply.