A 333-MHz dual-MAC DSP architecture for next-generation wireless applications
Ravi K. Kolagotla, José Fridman, M.M. Hoffman, William C. Anderson, B.C. Aldrich, David Witt, Markus Allén, R.R. Dunton, Len Booth · 2002
We introduce the first DSP core developed at the Analog Devices and Intel Joint DSP Development Center. The 16-bit fixed-point core combines some of the best features of traditional DSPs and micro-controllers and compares favorably with dual-MAC DSPs on DSP specific benchmarks and with micro-controllers on micro-controller specific benchmarks. In addition, the core supports a rich set of alignment independent packed byte instructions to enable an efficient implementation of 3G algorithms in next-generation wireless applications. The deep and fully interlocked pipeline allows the core to run at 333-MHz in the 0.18-/spl mu/m TSMC process.