A Power Modeling and Estimation Framework for VLIW-based Embedded Systems
Luca Benini, Davide Bruni, Mauro Chinosi, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon · 2001
Abstract. In this paper, a framework for modeling and estimating the system-level power consumption for embedded VLIW (Very Long Instruction Word) architectures is proposed. Power macro-models have been developed for the main components of the system: namely the core, the register file, the instruction and data caches. The models have been integrated within a hierarchy ofdynamic power estimation engines, at several abstraction levels. The main goal is to define a system-level simulation framework (i) to profile dynamically the power behavior during software execution and (ii) to provide a break-out ofthe power contributions due to the single components ofthe system. The proposed methodology has been applied to an industrial case study: the Lx family of scalable embedded VLIW processors, designed for multimedia and signal processing applications. Extensive validation ofthe proposed methodology has been carried out over a set ofmultimedia benchmarks for embedded applications. The experimental results have demonstrated an average accuracy of5 % ofthe instruction-level estimation engine with respect to the RTL engine, with an average speed-up offour orders of magnitude. 1