A Case for Vector Network Processors
Madhusudanan Seshadri · 2002
The explosive growth of Internet traffic and the increasing complexity of the functions performed by network nodes have given rise to a new breed of programmable microprocessors called network processors. However, network processor design is still in its infancy and has not reached a level of maturity commensurate with currently available commodity microprocessors. A variety of architectures are being proposed and implemented. Designs employing superscalar, chip multiprocessing (CMP), simultaneous multithreading (SMT) and very long instruction word (VLIW) techniques have been developed. In summary, current solutions attempt to exploit the abundantly available packet parallelism by using a multiple instruction multiple data (MIMD) approach. We propose a single instruction multiple data (SIMD) approach to packet processing. We highlight the inefficiencies in current network processor implementations and show how a vector processor can address these problems effectively. We tackle the problem of control flow variations in packet processing using a combination of intelligent hardware techniques and support for variable number of instruction streams (XIMD). Specifically, for the case of layer 3 routing, we show how a moderately sized cache of 2 KB can capture over 99% of routing table lookup results and enable efficient SIMD processing. We demonstrate the feasibility of our approach with vector algorithms for IP forwarding and network address translation. We also show how this approach can be extended to more complex packet processing applications.