A 15-Valued Algorithm for Test Pattern Generation
Akhtar Uz Zaman, Mahardi Kamalika Khusna Ali, Carlos R. P. Hartmann · 1989
In this report we present a new algorithm for detecting single stuck-at faults in combinational circuits. This algorithm is based on a I5-valued system and introduces several new concepts to make test generation more efficient. This 15-valued system allows us to impose all the constraints that must be satisfied in order to sensitize a single path. Consequently all deterministic implications are fully considered prior to the enumeration process. The resulting ability to identify inconsistencies prior to enumeration improves the possibility of quicker identification of redundant faults. Instead of sensitizing a single gate at a time, we sensitize subpaths by sensitizing all gates lying between successive fanout stems and then consider the deterministic implications of such a sensitization. We have introduced several speed-up techniques that effectively combine the information provided by the deterministic path sensitization and that obtained from the circuit topology. These techniques improve the efficiency of the enumeration phase by substantially pruning the search space. Copyright © July 1989 by A. M. Ali & C. R. P. Hartmann 1A. M. Ali is with the Department of Electrical & Computer Engineering, III Link Hall, Syracuse University, Syracuse, N.Y. 13244-1240. (e-mail: [email protected]) 2C. R. P. Hartmann is with the School of Computer and Information Science, Suite 4-116, Center for Science and Technology, Syracuse University, Syracuse, N.Y. 13244-4100. (e-mail: [email protected])