Low-complexity systolic multiplier over GF(2/sup m/) using weakly dual basis
Chiou‐Yng Lee, Ya-Cheng Lu, Erl‐Huei Lu · Asia Pacific Conference on Circuits and Systems · 2003
This paper offers a new bit-parallel systolic multiplier for GF(2/sup m/) using the weakly dual basis. The multiplier is composed of two units $multiplication and transformation. The structure of the multiplication unit includes m/sup 2/ cells, each cell is composed of one 2-input AND gate, one 2-input XOR gate and three/four 1-bit latches. The structure of the transformation unit is established by the 2-input XOR-tree. The latency of the multiplier only requires m+[log/sub 2/m] clock cycles.