A co-processor architecture for video scan-rate conversion and spatial/temporal noise reduction
Shaori Guo, Chien‐Hsin Lin, Zhengyu Zhang · 2005
A co-processor architecture for video scan-rate-conversion and noise reduction is presented. Both motion compensated and non-motion compensated deinterlacing and up-conversion algorithms are supported. This enables the co-processor to process both standard definition TV and high definition TV signals at low cost, offering a viable solution for consumer applications.