Customizable DSP architecture for ASIP core design
Yann Bajot, Habib Mehrez · 2002
We present in this paper a configurable DSP architecture and its associated software framework intended to be used in ASIP core design. This architecture aims to speed up the execution of a well-defined target application and minimize the hardware cost. It is based on a configurable and modular model that makes the most of intrinsic ILP of the application by the use of specialized functional units and VLIW instructions. Implementation results of a complex application, the GSM EFR encoder algorithm, shows the efficiency of the customized architecture.