Highly scalable 90nm STI bounded twin flash cell with local interconnect
N. Nagel, Dominik Olligs, V. Polei, S. Parascandola, H. Boubekeur, Long Giang Bạch, T. Muller, Matthias Straßburg, Stefan Riedel, P. Kratzert, D. Caspary, J. Deppe, Josef Willer, Norbert Schulze, Thomas Mikolajick, Karl Heinz Küsters, Assaf Shappir, E. Redmard, I. Bloom, Boaz Eitan · 2005
A 90nm Twin Flash memory cell with a size of 0.029/spl mu/m/sup 2//bit (3.5F/sup 2/) is presented. This cell is introduced first in a 1.8V, 2Gbit data flash. The Twin Flash technology is based on a shallow trench isolation (STI) bounded cell with local interconnect (LI) and serves for both advanced code and data flash storage memories. Beyond the 90nm node the scalability of the Twin Flash device is shown for 70 and 60nm node. The 90nm technology and its scaling follow the DRAM scaling path.