Low Space Complexity Bit-Parallel Shifted Polynomial Basis Multipliers using Irreducible Trinomials
Nam Su Chang, Chang-Han Kim · Information Security and Cryptology · 2010
Recently, Fan and Dai introduced a Shifted Polynomial Basis and construct a non-pipeline bit-parallel multiplier for . As the name implies, the SPB is obtained by multiplying the polynomial basis 1, , , by . Therefore, it is easy to transform the elements PB and SPB representations. After, based on the Modified Shifted Polynomial Basis(MSPB), SPB bit-parallel Mastrovito type I and type II multipliers for all irreducible trinomials are presented. In this paper, we present a bit-parallel architecture to multiply in SPB. This multiplier have a space complexity efficient than all previously presented architecture when n 2k. The proposed multiplier has more efficient space complexity than the best-result when 1 k (n+1)/3. Also, when (n+2)/3 k