Techniques for Memory Mapping on Multi-Core Automotive Embedded Systems
R. Amarnath · Research Repository (Delft University of Technology) · 2012
The demand to increase performance while conserving power has led to the invention of multi-core systems. The software until now had the convenience of gaining better performance over faster processors without any need for a change. The advances in the multi-core hardware have shifted the responsibility of software performance from hardware architects to software developers. To harness the true power of the multi-core, the software must utilize the available cores and memories. In this thesis, we focus on the issue of multi-core memory mapping which is an area of active research. The availability of multiple memories creates several possibilities for memory mapping. Further, with an increase in the number of memories and application parameters there is an exponential increase in the number of possible mappings. In this context, the challenge is to find techniques which automate the process of finding an efficient mapping for a given use case. The use case under consideration is an automotive software running on a multi-core electronic control unit (ECU). The proposed techniques help to optimize memory accesses by performing efficient memory mapping and reduce the runtime on a system which employs a non uniform memory access (NUMA) characteristic. The optimal memory mapping problem is NP-complete, it is tackled using integer linear programming (ILP) for smaller problems and heuristics to practically solve bigger problems. We also propose metaheuristics as an add-on to mitigate the drawbacks of ILP and heuristics. The experiments on the dual-core ECU hardware show that our flash memory mapping techniques reduce runtime by 2.76% when caches are enabled and up to 8.73% when caches are disabled. Also, the benefit of the ILP technique for RAM is 50.48% when compared to the placement of all the variables in global RAM.