Two-level hierarchical Z-Buffer for 3D graphics hardware
Cheng‐Hsien Chen, Chen‐Yi Lee · 2003
Memory bandwidth is a bottleneck in current 3D graphics systems. Traditional hidden surface removal Z-Buffer algorithm will result in memory bandwidth bottleneck in complex scenes. Its efficiency is low. Thus the hierarchical Z-Buffer, which is a reduced resolution Z-Buffer, is proposed to remove hidden surface more efficiently. Here we present a two-level hierarchical Z-Buffer algorithm, which is suitable for 3D graphics hardware implementation. It is not application visible and can be integrated with the rendering pipelines smoothly. A bit-mask cache is added to solve the hierarchical Z-Buffer update problem. Performance under different hierarchical block sizes, bit-mask cache sizes and hierarchical Z-Buffer accuracy are analyzed. The simulation results show that the overall Z-Buffer access bandwidth can be reduced from 10 to 35 percent.