State Machine Coding Styles for Synthesis
Clifford E. Cummings · 2002
This paper details efficient Verilog coding styles to infer synthesizable state machines. HDL considerations such as advantages and disadvantages of one-always block FSMs Vs. two-always Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL " [1], is a great paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper also offers in-depth background concerning the origin of specific state machine types. This paper, "State Machine Coding Styles for Synthesis, " details additional insights into state