A single chip digital TV LSI with a flexible 2D graphic processor utilizing an optimized memory architecture
Masahiro Yamada, E. Tomonaga, Ming–Chieh Lin, Jui‐Yi Hung · 2003
A single chip digital TV LSI including MPU, transport decoder, MPEG audio/video decoder, and graphic processor is described. This LSI utilizes dedicated RISC processors and advanced unified memory architecture with special arbitration algorithm, which enables optimal memory access operation.