Implementing a high-frequency pattern generator based on combinational merging
Charles A. Zukowski, Yusong Bai · 2003
A circuit architecture that can produce a high-frequency digital test pattern by merging a number of low-frequency patterns is implemented. This merging is accomplished using only delay elements and combinational logic, so the circuit's speed is not limited by clock constraints. Two prototype circuits using transistor-transistor logic (TTL) and emitter-coupled logic (ECL) are presented to demonstrate the approach and to explore implementation issues.>