Extensions to the VHDL RTL Synthesis Standard
Jim Lewis, Vinaya Kumar Singh · 2002
In 1999, IEEE 1076.6, Standard for VHDL Register Transfer Level Synthesis was first standardized. This standard places coding restrictions on model developers and language support requirements on synthesis tool developers. The goal of this standard is portability of RTL code on different synthesis tools. If a model developer writes code that is compliant to this standard, it will be supported by all compliant synthesis tools. The 1999 revision of this standard set the restrictions on tool vendors low with the intention of getting to portability quickly. Currently enhancements are being finalized for the next draft of the standard. Syntax enhancements include VHDL-93 support as well aliases and configurations to name a few. Semantic enhancements transition us from a template based semantic methodology to an algorithm based semantic methodology. One of the benefits of this is a richer, more flexible set of register coding styles. This paper discusses the enhancements and shows how they will help Joe Designer to efficiently write a wide variety of hardware elements at a higher level. We will also be asking for your support to encourage EDA vendors to support VHDL standards. 1.