Interconnect synthesis for systems on chip
Neal K. Bambha, Shuvra S. Bhattacharyya · 2004
We describe an algorithm for performing a joint scheduling /interconnect synthesis optimization for System-on-Chip (SoC) architectures. The algorithm is able to account for different distributions of long vs. short interconnect routes in an architecture. It is based on a genetic algorithm, and utilizes a graph isomorphism test to significantly pare the search space and increase the search efficiency.