Automatic Generation of Scheduled SystemC Models of Embedded Systems from Extended Task Graphs
Stephan Klaus, Sorin Alexander Huss, Timo Trautmann · Kluwer Academic Publishers eBooks · 2006
Based on an abstract specification denoted as extended Task Graph (eTG) and allocation, binding, and scheduling information, a scheduled and executable SystemC transaction level model (TLM) of distributed embedded systems is generated. Therewith, the whole communication and run-time control is being automatically produced, and the SystemC simulation kernel allows a timely execution and timing validation of the specification. A further benefit of the proposed specification model is the consistent definition of interfaces, which supports the encapsulation of blocks and enables the reuse of IP cores, thus leading to a hierarchical specification of distributed embedded systems.