Reconfigurable Processing Module
Kevin Somervill, Robert F. Hodson, Robert L. Jones, John A. Williams · NASA Technical Reports Server (NASA) · 2005
To accommodate a wide spectrum of applications and technologies, NASA s Exploration System's Missions Directorate has called for reconfigurable and modular technologies to support future missions to moon and Mars. In response, Langley Research Center is leading a program entitled Reconfigurable Scaleable Computing (RSC) that is centered on development of FPGA-based computing resources in a stackable form factor. This paper details architecture and implementation of Reconfigurable Processing Module (RPM), which is key element of RSC system. The RPM is an FPGA-based, space-qualified printed circuit assembly leveraging terrestrial/commercial design standards into space applications domain. The form factor is similar to, and backwards compatible with, PCI-104 standard utilizing only PCI interface. The size is expanded to accommodate required functionality while still better than 30% smaller than a 3U CompactPCI(TradeMark)card and without overhead of backplane. The architecture is built around two FPGA devices, one hosting PCI and memory interfaces, and another hosting mission resources; both of which are connected with a high-speed data bus. The PCI interface FPGA provides access via PCI bus to onboard SDRAM, flash PROM, and resources; both configuration management as well as runtime interaction. The reconfigurable FPGA, referred to as Application FPGA - or simply the application - is a radiation-tolerant Xilinx Virtex-4 FX60 hosting custom specific logic or soft microprocessor IP. The RPM implements various SEE mitigation techniques including TMR, EDAC, and configuration scrubbing of reconfigurable FPGA. Prototype hardware and formal modeling techniques are used to explore performability trade space. These models provide a novel way to calculate quality-of-service performance measures while simultaneously considering fault-related behavior due to SEE soft errors.