Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware.
Kris Gaj, Paweł Chodowiec · 2000
The results of implementations of all five AES finalists using Xilinx Field Programmable Gate Arrays are presented and analyzed. Performance of four alternative hardware architectures is discussed and compared. The AES candidates are divided into three classes depending on their hardware performance characteristics. Recommendation regarding the optimum choice of the algorithms for AES is provided.