A modular analog CMOS LSI for feedforward neural networks with on-chip BEP learning
Y. Wang · 1993 IEEE International Symposium on Circuits and Systems · 2002
A modular design approach for analog CMOS implementation of a feedforward neural net with on-chip backward error propagation (BEP) learning is proposed. Two LSI prototype chips have been designed and sent for fabrication in 2.2 /spl times/ 2.2 mm/sup 2/ using a standard 2/spl mu/m CMOS technology. The first chips integrates two 3 /spl times/ 3 synapses multiplications, integrations, and storages. The synapse chips can be cascaded horizontally to increase the number of inputs per layer, and vertically to add the number of neurons per layer. The second chip integrates three variable-gain neurons with adjustable-gain sigmoidal activation function and the first derivative of the sigmoidal function. Custom VLSI layout reduces the layout area of the processing elements, which in turn increases the expected network density. The modular architecture of the circuits makes it possible to increase the size of the network by interconnecting multiple modular chips.>