Finely tunable standard cells for high-speed ASMIC
Toshinari Takayanagi, Takeaki Sakurai, K. Sawada, K. Nogami, Tetsuya Iizuka · International Symposium on VLSI Technology, Systems, and Applications · 2003
A finely tunable standard cell (FTSC) method is introduced to cope with the complexity and high-speed nature of application-specific memory ICs (ASMICs). The method is applied to an integrated cache memory, a typical high-speed ASMIC, and achieves address-to-hit delay of 18 ns, which is comparable to that of a standard full-custom static RAM (SRAM). The FTSC offers the sizing capability of MOSFETs and stable delay elements composed of poly-Si resistors.>