Functional testing and constrained synthesis of sequential architectures
G. Buonanno, Franco Fummi, Donatella Sciuto · 1993 IEEE International Symposium on Circuits and Systems · 2002
A new approach is presented for test pattern generation for finite state machines and the relationships with their gate level implementation. The results on a study on implementation constraints that will guarantee a fixed fault coverage are presented. The proposed techniques are checked through some MCNC benchmarks and their results are compared with previous papers.>