Labyrinth: a homogeneous computational medium
Frederick C. Furtek, G. Stone, Ian W. Jones · 2002
As a RAM-based reconfigurable logic array, Labyrinth provides the flexibility and malleability of software with the performance of a dedicated circuit. With a single bit register and a half adder per cell, the architecture is optimized for register intensive, massively parallel algorithms. The fine-grained, highly-symmetric architecture scales very naturally and facilitates compact circuit layouts. A 64-cell test chip has been successfully built and tested, and a 4096-cell chip is in the final stages of preparation for fabrication.>