A new self-test structure for at-speed test of crosstalk in SoC busses
Jun Yang, Hu Chen, Youhua Shi, Zhe Zhang, Longxing Shi · 2002
The use of deep submicron process technologies increases the probability of crosstalk faults in the bus of a system-on-a-chip (SoC). Though a self-testing methodology based on MA fault model has been developed, its area overhead of test logic is excessive. This paper proposed a new error detector (ED) and new test patterns whose overhead is decreased down to only approximately 50% of the old methodology on average. A behavior fault simulation is used to validate the self-testing structure described.