Vertex cache of programmable geometry processor for mobile multimedia application
Kyusik Chung, Chang-Hyo Yu, Lee‐Sup Kim · 2006
Vertex cache of programmable geometry processor is proposed and implemented. The proposed vertex cache is organized into pre-TnL vertex cache and post-TnL vertex cache. The pre-TnL vertex cache reduces 32.8% geometry bandwidth by reusing fetched vertices with 32 entries. The post-TnL vertex cache improves the performance of a geometry processor by reusing recently processed vertices with 16 entries. Its performance gain is 1.69 on the average. 1.9k logic gates and 12kB single port SRAM are required for their implementation in 0.18 /spl mu/m CMOS technology.