The impact of routing cache on high-performance switches
Michihiro Koibuchi, Shinichi Ishida, Hiroaki Nishi · International Conference on Optical Internet · 2012
Large parallel applications become sensitive to communication latencies, suggesting the need for low-latency networks in high-performance computer systems. Switch delay dominates network latencies, especially for a large number of small transfer data. To reduce the network latencies, we exploit routing cache on a switch. Routing decision based on off-chip CAM(Content Addressable Memory)-based table lookup imposes a significant delay, however, using on-chip small routing cache can bypass it when it hits. Our simulation results showed that 1,024-entry routing cache improves not only up to 13% of packet latency but also up to 18% of network throughput compared with no-cache switches.