Architectural Support for Runtime 2D Partial Reconfiguration.
Fei Wang, Jack Jean · ERSA · 2006
Traditional FPGA architectures can potentially allow the dynamic swap in and out of hardware tasks through 2D partial reconfiguration. A segmented bus structure is proposed to be superimposed on such architectures. Its purpose is to support connections between on-chip hardware tasks, or between hardware tasks and chip IO pads. The required area overhead is also estimated.