Architecture Design Space Exploration for Streaming Applications Through Timing Analysis
Maarten H. Wiggers, N.K. Kavaldjiev, Gerard J.M. Smit, Pierre G. Jansen · University of Twente Research Information · 2005
Abstract. In this paper we compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN\\2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the application’s throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.