Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited)
Thorsten Jungeblut, Johannes Ax, Gregor Sievers, Boris Hübener, Mario Porrmann, Ulrich Rückert · PUB – Publications at Bielefeld University (Bielefeld University) · 2011
In this work we discuss the resource efficiency of scalable processor architectures for software-defined radio (SDR) based applications.The development of resource efficient processor architectures is based on a two-staged design flow using a high level processor specification as a reference.This design-flow has been used to perform a comprehensive design-space exploration of algorithms from various application scenarios.As a result the 4-issue VLIWarchitecture CoreVA has been implemented.The finegrained parallelism of this architecture allows for performance gains of up to a factor of three to four for the analyzed application scenarios.From the design-space exploration on system level dedicated hardware accelerators have been derived.The hardware accelerators proposed in this work improve the energy efficiency by a factor of 6 to 43.To further improve the performance of the system, the single-core based approach is extended to network-on-chip (NoC) level.As an example, an IEEE 802.11b application has been mapped to a cluster of four processor cores reducing the processing time of the algorithm by up to 60 %.