A design for FPGA implementation of the probabilistic neural network
G. Minchin, Anthony Zaknich · 2003
A design concept is introduced for the implementation of the probabilistic neural network classifier using standard binary field programmable gate array logic. It is an efficient hardware design concept which substitutes fixed point binary valued vector components for real valued ones and uses a top hat spherical basis function in conjunction with a city block distance measure without significantly affecting classifier performance for some practical problems.