Architectures and algorithms for parallel updates of raster scan displays
Satish Gupta · 1982
P'33615-78-C-1551. The views and conclusions contained in this document are those of the authors and should not bc interpreted as representing the official policies, either expressed or implied, of the The frame buffer memory organization is the key to achieving high display performance. Traditional frame buffer designs use the scan-line organization which allows several pixels along the length of a scan-line to be updated together. This thesis advocates the symmetric square organization which allows the access of square regions of the display. This organization is based on the belief that the regions of the display which are commonly accessed simultaneously are no more likely to be tall and thin than to be short and wide. The square memory organization is studied for representative display applications and is shown to be indeed better than the scan-line organization. Based on the algorithms for these applications, a display design is presented. This design uses one custom designed LSI chip, 64 copies of which are required to implement the frame buffer memory system. TABI,Eo[: CONTENTS