Area-efficient area pad design for high pin-count chips
L. Luh, J. Chroma, Jeffrey T. Draper · 2003
This paper presents an area pad layout method to efficiently reduce the space required for interconnection pads and pad drivers. Unlike peripheral pads, area pads use only the top metal layer and therefore allow active circuitry to be laid out underneath. With identical functional elements grouped together, a group of pad drivers share the same well and can be placed tightly together. The use of silicided diffusion reduces the well contact to diffusion contact spacing requirement. By taking advantage of this spacing requirement and using serpentine gate layout, a driver's size can be effectively reduced without reducing the driving capacity. An embedded multicomputer router interface chip has been implemented using these techniques and has achieved 554 pads in a 9 mm/spl times/6 mm chip with a 0.8 /spl mu/m single-poly 3-metal N-well CMOS process.