A low-power bit-serial multiplier for finite fields GF(2/sup m/)
Johann Großschädl · 2002
This paper presents a bit-serial architecture for efficient addition and multiplication in binary finite fields GF(2/sup m/) using a polynomial basis representation. Moreover, a low-voltage/low-power implementation of the arithmetic circuits and the registers is proposed. The introduced multiplier operates over a variety of binary fields up to an order of 2/sup m/. We detail that the bit-serial multiplier architecture can be implemented with only 28m gate equivalents, and that it is scalable, highly regular and simple to design.