A 9.6 GigaByte/s throughput plesiochronous routing chip
A. Mu, J. Larson, R. Sastry, Thomas Wicki, W. W. Wilcke · 2002
The design of a very high performance routing chip with six bi-directional link ports and an aggregate sustained throughput of 9.6 GByte/s is described The routing chips will form the switching fabric of a cache-coherent, Non-Uniform Memory Access (cc-NUMA) multiprocessor system. The key elements of the chip are a non-blocking internal crossbar; synchronization circuits for plesiochronous operation (i.e. no central system clock required) and reliance on hardware end-to-end error checking. The chip has recently been taped out.