Dynamic configuration using pyramidal architecture FPGA and a built-in RISC processer
Mohamad Sawan, C.E. Rabel · 2002
This paper presents a new pyramidal architecture FPGA (PARC) including a RISC processor dedicated for fast dynamic configurations systems. The PARC FPGA consists of a large number of fine-grained array of optimized heterogenous logic blocks and a new pyramidal structure with three hierarchical levels. The proposed FPGA is a reprogrammable SRAM based device. The built-in processor is designed as a 16-bit microprocessor with a reduced instruction set (32 instructions), hardware and software interrupts, and 16-bit address and data buses. The whole device has been developed with Synopsys design automation CAD tools, using VHDE and the 0.8 /spl mu/m BiCMOS technology from Nortel to operate at a 50 MHz clock frequency.