Mapping the MD5 hash algorithm onto the NAPA architecture
Jeffrey M. Arnold · 2002
National Semiconductor's Adaptive Processing Architecture (NAPA) integrates a Fixed Instruction set Processor (FIP), an Adaptive Logic Processor (ALP), memory and other support circuitry into a single reconfigurable computing device. In the NAPA1000 the FIP is a small 32-bit RISC microprocessor and the ALP is a 64/spl times/96 array of fine grain reconfigurable logic cells. The NAPA1000 also contains two banks of 2048/spl times/32 Pipeline Memory Array (PMA), eight banks of 256/spl times/8 Scratchpad Memory Array (SMA), and one bank of 1024/spl times/32 Local Memory Array (LMA). External to the NAPA1000 are two banks of DRAM and an interface to a host computer. The Toggle Bus transceiver is the interface to a multi-stage interconnect network, and is capable of performing arbitrary reflections and rotations on 32-bit words. The Reconfiguration Pipeline Control unit (RPC) can also serve as a DMA engine.