LUT-based MPGAs for fast turnaround time conversion flow
F.-J. Veredas, M. Scheppler, Bumei Zhai, H.-J. Pfleiderer · 2006
This paper presents two LUT-based MPGA architectures. The first MPGA architecture preserves the logic and the hierarchical routing interconnect scheme of an FPGA. The second MPGA architecture has a new regular routing interconnect scheme. Our experiments reveal an average area reduction of 97% in the second architecture compared to the first architecture and 81% in respect of an FPGA. The shrinking factor yields a reduction of 94% in the interconnect delay and 75% in the effective capacitance of a one-length wire. A study in one industrial design shows that the first architecture and the FPGA have 40% of more total wire-length. The second architecture has a potential reduction in dynamic power consumption.