Third-generation architecture boosts speed and density of field-programmable gate arrays
R.B. Ravel · Third Annual IEEE Proceedings on ASIC Seminar and Exhibit · 2002
A third-generation family of field-programmable gate arrays (FPGAs) that utilizes a combination of architectural and process improvements and features up to twice the density and speed of currently available FPGA devices is discussed. The architecture allows complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. User-configurable on-chip static memory resources further contribute to the high integration levels available to users of the third-generation devices.>