Diagnosing Delay Faults in Combinational Circuits under the Ambiguous Delay Model
Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu · 1999
SUMMARY In our previous paper [9] we presented a pathtracing method of multiple gate delay fault diagnosis in combinational circuits. In this paper,we propose an improved method that uses the ambiguous delay model. This delay model makes provision for parameter variations in the manufacturing process of ICs. For the effectiveness of the current method,we propose a timed 8-valued simulation and some new diagnostic rules. Furthermore,we introduce a preparatory process that speeds up diagnosis. Also,at the end of diagnosis,additional information from the results of the preparatory process makes it possible to